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  劉時(shí)友 2009-03-09 00:00:00

  Image Processing System Components The system hardware mainly includes illumination system， CCD high-speed photo Camera， frame grabbers， image processing DSP chip card and executing agencies CPLD (complex programmable logic device)， etc.; and software embedded in the image Treatment card， that contains different effective fiber detection and recognition algorithms. The algorithm can be Implementation of the image in a variety of different fiber analysis， identification， statistics and decision-making. High Speed， high anti-interference of the image processing hardware to ensure that the system in industrial applications Real-time and reliability requirements. 2.1 System hardware block diagram The design program for the DSP + CPI D based on the structure of digital images Processing system. It requires the completion of image acquisition， digital processing， image Office Rationale， image analysis， image display and other functions. This system to TI's TMS320DM642 as the host processor. The overall work flow system as follows: sweep on both sides of the line CCD camera Put image signal collected by the TVP5150 video decoder chip conversion For ITu - RBT. 656 format， the embedded sync signal is sent to the DM642 mouth of the VP. Synchronous line images， are shown simultaneously， and field sync signal Are embedded in video data stream. For chip storage resources are limited high - Speed DSP， stored video data to another external storage space. In order to mention High real-time processing capability， data transmission by the EDMA completed， CPU Used only for data. Collecting video data stored by the EDMA SDRAM， or put data from the video channel sent to the chip RAM In computing. DSP (DM642) for image analysis， identification， set Algorithm and so on， and deal with the different classification of fiber identification， by the EDMA， SAA7121H video encoder， its signal is converted to PAL (50 HZ) format or NTSC (60 HZ) format to the external LCD screen for 顯示. SDRAM on one of DM642's the corresponding mapping address CE0 Space， the use of two 32-bit data bus of synchronous dynamic RAM， a high 32 stored in RAM in a low 32 is stored in another film RAM， meet the DM642 64-bit data bus requirements. SDRAM CE0 at specific sub-space defined as: 0x80000000H 1 0x81FFFFFFH. Curing System at FLASH code， the FI ASH at CE1 subspace occupied by the specific spatial location is: 0x90000000H 1 0x9007FFFFH. DM642 only 20 External address bus， so the maximum addressable space CE1 range of 1 M × 8 bit， SEED-VPM642 board apart from the distribution of sub-space CE1 FLASH give away， but also allocated to the status / control register， UAR - TA， UARTB such as the use of resources， only one of FLASH sub-CE1 Spaces of the former half of the address space， that is the largest addressable range of 512 K × 8， while FLASH design capacity of the 4 M × 8 spaces， so Technical implementation of pagination using FLASH visit soon the entire 4 M × 8-bit FLASH is divided into eight 512 K × 8-bit page， and pages to Site PA21， PA20， PAl9 provided by the page address register (page and Register at the site in CPLD). CF card access at EMIF card CE2 Space， used to store and identify the characteristics of the results of the Treasury. CPLD are in the traditional PAL， GAL developed from the foundation up Of. FPGA compared with， CPLD bus more suitable for computer control， Storage controller， DMA controller， CACHE controller， graphics control Such as I / O-intensive applications， and have no need for external configuration ROM， when Extension of predictable characteristics. CPLD generally based on the current E2 and FLASH erasable electric technology， achieve more than 100 write cycle. Test Consideration to the system design， selection of a model of CY37O64P1OO Complex programmable logic device， the working voltage of 3.3 V. 2.2 Identification of different software development defibrase In software development， to the C6000 the CCS (Code Composer Studio) Integrated Development Environment for the main line. Applies to C6000 Series C60OO the CCS are the mainstream of DSP development tools， The current 3.3 version has been launched. CCS is a Introduces TI integrated DSP software development tools. At an open plug-ins (plug-in) structure， CCS within Department integrates the following software tools: (1) C6000 code generation tool (including the C compilation C6000 ， Assembler optimizer， assembler and connectors); (2) software simulator; (3) real-time software foundation DSP / BIOS; (4) between the host and the target real-time data exchange software， RT - DX: (5) real-time analysis and data visualization software. At CCS， the developers of the software can edit， compile， tune Test， code performance testing and project management of all work. In addition， it Provides real-time analysis and data visualization capabilities， greatly reduced the DSP The difficulty of system development so that developers can concentrate on the application of open Hair on

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